Intel Processes 1M High-NA EUV Wafers, Leads Industry

One Million High-NA Wafers

Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners. This achievement occurred less than two and a half years after the company’s first tool was assembled. The one-million-wafer figure includes wafers processed during tool installation and certification, research and development, and production. Earlier this year, Intel certified the use of High-NA EUV scanners for its 18A process technology. Consequently, these tools are currently used to manufacture some of Intel’s Panther Lake processors.

The company currently operates two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel was processing around 30,000 wafers using its High-NA EUV tools. The increase from 30,000 wafers by February 2025 to over a million by September 2026 represents an enormous increase in cumulative High-NA utilization. Since Intel’s fleet expanded from two EXE:5000 systems to three, and now includes the much faster EXE:5200B, the million-wafer milestone is both a fleet and process-maturity achievement that Intel has reached first in the industry.

The significance of this milestone is further highlighted by data from ASML. In April, ASML announced that all High-NA EUV scanners shipped by that time had processed over 500,000 wafers while achieving over 80% availability. This means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.

The Challenge of Stitching

For now, Intel intends to use industry-standard 6-inch photomasks. These masks can expose 26×16.5 mm half-fields, which requires field stitching for larger chips. Conventional 0.33-NA EUV uses 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification. As a result, the same 6×6 mask provides only approximately 26×16.5 mm on the wafer.

Large dies that fit within a conventional 26×33 mm EUV field must be exposed as two half-fields using High-NA EUV. This process is called stitching. While stitching is a workable near-term solution, it has several drawbacks. First, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Second, chip designs must account for stitching and be developed with it in mind, which limits floor planning freedom. Third, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, potentially creating defects and reducing yields. This is a particularly costly problem for large CPU and GPU dies.

Progress Toward 6×12 Masks

To avoid using stitching, the industry—led by Intel—plans to shift to larger 6×12 masks. These masks would enable a 26×33 mm full field in one exposure. While this appears straightforward on paper, making the mask twice as long represents an enormous ecosystem change. Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem. This includes mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems.

Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks. This will make the transition a major retooling effort across the semiconductor supply chain. Neither ASML nor Intel has confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks. According to ASML’s roadmap, all future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching.

It remains to be seen whether the industry moves to larger 6×12-inch photomasks. However, Intel appears to be the main advocate for changing the mask standard that has defined projection lithography infrastructure for decades. If this effort comes to fruition, Intel will likely have a considerable first-mover advantage over its industry peers. It would define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.