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Reviews 08 September 2026 7 min read

Arm Neoverse CSS N4 'Ranger' Debuts

Arm unveils the next-gen Neoverse CSS N4 'Ranger' platform, featuring up to 128 cores per die on TSMC N3P, alongside new AGI chip deployments.
Author: Зануда PC
Arm Neoverse CSS N4 'Ranger' Debuts

Arm has officially unveiled its next-generation Neoverse CSS N4 platform, codenamed Ranger, a semi-custom compute subsystem designed for cloud infrastructure. Built on TSMC's N3P process, the platform supports up to 128 Neoverse N4 cores per die, marking a significant expansion in core density and performance efficiency for data center workloads optimized for performance per watt.

The announcement represents a substantial evolution in Arm's Compute Subsystem (CSS) program, which allows hyperscalers and enterprise customers to design semi-custom silicon based on Arm's intellectual property. Unlike standard off-the-shelf processors, the CSS platform enables partners to configure specific components, including core count, cache hierarchy, input/output interfaces, and connectivity options, to meet precise workload requirements. This flexibility has previously powered diverse implementations, ranging from cloud CPUs at Azure and Google Cloud to data path units (DPUs) at Nvidia and Intel.

According to Arm, the Neoverse CSS N4 supports a configuration range of eight to 128 Neoverse N4 cores, with clock speeds reaching up to 3.8 GHz. While Arm did not specify the exact clock speeds for every possible core count configuration, it is implied that frequencies may decrease as core density increases to manage power and thermal constraints. At the system level, the platform is designed to scale beyond the single-die limit of 128 cores. This is achieved through support for multi-chiplet and multi-socket designs, utilizing the Universal Chiplet Interconnect Express (UCIe) for chip-to-chip interconnects, as well as partner-specific proprietary interconnects.

Memory and cache architecture are central to the N4's design philosophy. The platform supports both DDR5 and LPDDR6 memory standards, offering flexibility for different bandwidth and capacity needs. Each die can feature up to 256 MB of L3 cache. For local caching, the architecture includes up to 2 MB of L2 cache per core, alongside 64 KB of L1 instruction cache and 64 KB of L1 data cache per core. On the I/O front, the subsystem supports up to 128 lanes of PCIe 7.0 or 6.0, as well as CXL 4.0, facilitating high-speed data movement and memory expansion.

Comparing the new platform to its predecessor highlights the magnitude of the upgrade. The previous generation, Neoverse CSS N2, was limited to a maximum of 64 cores, 1 MB of L2 cache per core, and 64 MB of L3 cache. It supported DDR5 or LPDDR5 memory and offered 64 lanes of PCIe 5.0 or CXL. The jump to 128 cores, doubled L2 cache per core, and quadrupled L3 cache per die represents a significant leap in architectural density and capability.

Arm claims that with 128 cores running at 3 GHz and 2 MB of L2 cache per core, the Neoverse CSS N4 delivers twice the socket performance of the Neoverse N3. Additionally, the platform offers 1.25 times the performance per watt and 1.75 times the memory bandwidth compared to the previous generation. These metrics are particularly relevant for cloud providers seeking to reduce operational costs while maintaining high throughput for scalable workloads.

It is important to distinguish the role of Arm's N-series cores from its V-series cores. The N-series is optimized for performance per watt, making it suitable for high-density, cost-efficient cloud deployments. In contrast, the V-series targets maximum absolute performance. For example, Arm utilized Neoverse CSS V3 building blocks for its own AGI CPU, while Nvidia used Neoverse V2 for its last-generation Grace CPU. AWS has employed Neoverse V-series cores for its Graviton chips, and Google Cloud uses them for Axion. N-series cores are typically found in less performance-intensive accelerators, such as Intel's IPU Adapter E2100 built on Neoverse N1, or in cloud workloads like Microsoft's Azure Cobalt 100, which was based on Neoverse N2. The newer Azure Cobalt 200 has moved to Neoverse V3, reflecting a shift toward higher performance in some Azure deployments.

Details regarding the specific Neoverse N4 cores, codenamed Dionysus, remain limited. Arm's 2024 roadmap also indicated the upcoming Neoverse CSS V4, codenamed Vega. Unlike traditional announcements from Intel, AMD, or other partners, the Neoverse N4 cores will not appear in consumer or standard server products immediately. The announcement is directed at partners building on the CSS platform, leveraging Arm's validated building blocks to create semi-custom silicon rapidly. Arm has not yet announced specific partners for the N4, though historically, only a few large CSS contracts are required to drive adoption.

Additional Arm AGI CPU Deployments

Alongside the Neoverse CSS N4 announcement, Arm revealed additional deployments of its own AGI chip, which is built with Neoverse V3 cores. The company disclosed that Oracle and ByteDance will deploy AGI chips, joining previously announced deployments at Meta, Lenovo, SAP, OpenAI, Cloudflare, and others. This expansion underscores Arm's strategy to establish its own silicon in the data center market, rather than solely licensing IP to partners.

Despite extensive discussion about the AGI chip, including a detailed architectural breakdown at Hot Chips, real-world performance numbers have not yet been published. This is not uncommon for recent Arm-based chips; for instance, performance comparisons for Microsoft's Azure Cobalt 200 and AWS' Graviton5 are currently limited to generation-over-generation estimates. Arm has described the AGI as offering "more than 2x the performance per rack compared to the latest x86 systems," but these claims are based on internal estimates rather than independent benchmarks.

The AGI is a dual-die CPU featuring up to 136 Neoverse V3 cores and up to 272 MB of L3 cache, capable of clocking up to 3.7 GHz. It is built on a 3nm node and supports up to 6 TB of memory capacity per chip, running at up to DDR5-8800. A key architectural difference compared to AMD and Intel designs is Arm's decision to integrate memory and I/O on the same die as the compute cores. Arm states that this design choice leads to sub-100ns memory latency, potentially improving data access speeds for latency-sensitive applications.

This marks Arm's first attempt at its own production silicon, although the company has positioned the AGI as a vehicle for demonstrating the broader applications of Arm in the data center. The primary business model remains the licensing of IP to partners like Microsoft, Nvidia, Meta, and Google Cloud, who build custom chips based on Arm's architecture. The introduction of the AGI and the Neoverse CSS N4 platform signals a dual-track strategy: continuing to empower partners with flexible, high-efficiency building blocks while simultaneously establishing Arm's own presence in the high-performance data center segment.

The Neoverse CSS N4 platform, with its support for up to 128 cores per die and advanced memory and I/O capabilities, is poised to influence the next generation of cloud infrastructure. As hyperscalers continue to seek efficiency and scalability, the semi-custom nature of the CSS program allows for tailored solutions that can address specific workload challenges. The integration of UCIe and CXL 4.0 further positions the platform for future-proofing, enabling seamless expansion and high-speed interconnects in complex data center environments.

While the N-series is not intended to compete directly with high-performance V-series cores in raw throughput, its focus on performance per watt makes it an attractive option for large-scale deployments where energy efficiency is a primary concern. The ability to scale beyond 128 cores through multi-chiplet designs also provides a pathway for higher aggregate performance without sacrificing the efficiency benefits of the N-series architecture. As Arm continues to expand its ecosystem, the Neoverse CSS N4 will likely play a crucial role in shaping the future of cloud computing infrastructure.

The lack of immediate consumer-facing products for the Neoverse N4 cores is consistent with Arm's historical approach to the N-series. These cores are designed for specific, high-volume, efficiency-focused applications rather than general-purpose high-performance computing. The partnership model, where Arm provides the IP and partners handle the design and manufacturing, ensures that the resulting silicon is optimized for the partner's specific needs. This collaborative approach has been a key driver of Arm's success in the data center market, and the Neoverse CSS N4 is expected to continue this trend.

In conclusion, the debut of the Neoverse CSS N4 'Ranger' platform represents a significant step forward in Arm's data center offerings. With its high core density, advanced memory support, and scalable architecture, it provides a robust foundation for next-generation cloud infrastructure. The simultaneous expansion of Arm's AGI chip deployments further highlights the company's ambition to compete in the high-performance segment while maintaining its core strength in efficient, scalable computing. As the industry continues to evolve, the interplay between Arm's IP licensing and its own silicon will be a critical factor in determining the future landscape of data center computing.

Article author

Зануда

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