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Hardware 04 October 2026 • 2 min read •

SEMIFIVE and Mobilint Develop Robotics AI Chip with LPDDR6 and PCIe 6.0 Support

South Korean companies SEMIFIVE and Mobilint have announced a project for a specialized AI chip for robotics, featuring LPDDR6, PCIe 6.0, and UCIe-S chiplet interconnect.
Author: Гика • PC •
SEMIFIVE and Mobilint Develop Robotics AI Chip with LPDDR6 and PCIe 6.0 Support

South Korean firms SEMIFIVE and Mobilint have entered into a turnkey agreement to develop a specialized AI chip tailored for robotics and local AI processing (On-Device AI). The project is part of the state-funded "K-On-Device AI Semiconductor Technology Development" program. The goal is to create processors capable of performing AI computations directly on the device, reducing reliance on external servers and constant network connectivity. Potential applications include agricultural robots that require immediate processing of camera and sensor data.

Modular Architecture and High-Speed Interfaces

The project's technical roadmap highlights a significant leap in connectivity. The upcoming chip is slated to support LPDDR6 memory and the PCI Express 6.0 interface. By adopting PCIe 6.0, which offers double the raw data rate of PCIe 5.0 (reaching up to 256 GB/s bidirectional bandwidth in a x16 configuration), the platform will be able to interface with high-speed components like sensor hubs, additional accelerators, and network controllers.

A key technical highlight is the inclusion of UCIe-S (Universal Chiplet Interconnect Express). This open standard facilitates communication between multiple chiplets within a single package. Instead of relying on a single large monolithic die, the use of UCIe-S suggests a modular System-in-Package (SiP) approach, allowing different functional blocks—such as compute or I/O dies—to be integrated more flexibly.

Evolution from the ARIES Platform

This collaboration follows the success of the ARIES AI accelerator, which entered mass production in early 2025. However, the new robotics-focused chip represents a major generational jump. While ARIES was built on a 14nm process and utilized LPDDR4X and PCIe 4.0 x8, the new project moves toward much higher bandwidth and more advanced interface standards, though specific NPU architecture and manufacturing nodes remain undisclosed.

Currently, the project is in its early stages. SEMIFIVE and Mobilint have not yet confirmed a tape-out date, a specific manufacturing process, or the target TOPS (Tera Operations Per Second) performance. Nevertheless, the direction is clear: a shift toward high bandwidth, low latency, and power efficiency, catering to the growing demand for autonomous systems that must operate reliably in environments without consistent cloud access.

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Гика

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