OpenAI and Synopsys develop GPT-Synopsys to automate chip design via EDA tools
OpenAI and Synopsys have announced a multi-year partnership to develop GPT-Synopsys. This specialized AI model is intended to go beyond simple text generation by directly operating professional Electronic Design Automation (EDA) tools to perform iterative semiconductor design optimization.
Automating PPA and Engineering Workflows
Unlike general-purpose LLMs that might only assist with scripting or debugging, GPT-Synopsys is designed to function as an agent within the engineering stack. Synopsys states that developers will be able to set targets for PPA (Power, Performance, and Area), and the system will autonomously call EDA tools, interpret the results, and implement design changes. This includes critical tasks such as timing analysis and verification closure.
According to Reuters, OpenAI will initially pay licensing fees to use Synopsys software for training the model. Once the product is launched, the companies plan to share revenues through a collaborative commercial model. The system is expected to run on OpenAI's infrastructure while integrating with Synopsys.ai and the company's Autopilot platform.
Data Security and the Human Element
Given the sensitive nature of semiconductor IP, Synopsys has explicitly stated that customer-specific design data will not be used to train GPT-Synopsys. The company promises encrypted data transmission and storage, alongside configurable rules for auditing and access control. However, the specific technical architecture for ensuring total isolation within OpenAI's cloud environment has not yet been detailed.
It is important to note that GPT-Synopsys is not intended to replace the traditional sign-off process. As reported by Reuters, all AI-generated design iterations must still undergo rigorous verification using deterministic classical computational methods to ensure physical correctness. Rather than replacing engineers, the technology aims to automate the manual iterations between tools, acting as a highly efficient assistant in the complex chip development lifecycle.