Arm and Lattice develop new server platform: FPGAs to handle security and management in AI data centers
A new architecture combining Arm AGI processors, Lattice FPGAs, and AMI firmware aims to provide modularity and security for AI infrastructure via the LTPI standard.
Rather than competing on raw compute power, Arm, Lattice Semiconductor, and AMI are focusing on the infrastructure that makes that power possible. The companies have announced a new server platform for AI data centers, where programmable logic devices (FPGAs) will handle security, management, and component communication.
Modern AI servers are growing in complexity, not just because of accelerators, but because of the need to ensure stable and secure operation. The new architecture, set to be demonstrated at the OCP Global Summit in October 2026, proposes a division of labor: while Arm AGI processors handle the heavy lifting of AI workloads, Lattice solutions will manage the supporting infrastructure.
The core of this partnership lies in using FPGAs as so-called "companion chips." They will work alongside the main processor and the Baseboard Management Controller (BMC), complementing both with additional security and connectivity functions rather than replacing them. This provides server manufacturers with flexibility: if security requirements or interfaces change, FPGA logic can be reconfigured without the need to develop a completely new specialized chip for every hardware platform.
Modularity and Security via FPGA
Lattice views its FPGAs as an additional hardware layer that can implement monitoring and security functions independently of the CPU. This architecture can help distribute security-critical tasks to separate components. Notably, since AMI is now part of Lattice Semiconductor, the collaboration integrates both programmable hardware and firmware technologies, which could potentially simplify the coordination between control logic and management software.
LTPI Standard and Modular Approach
A key technical focus is the support for LTPI (LVDS Tunneling Protocol and Interface), an open interface technology from the Open Compute Project. This interface will connect the Host Processor Module (HPM) with the Datacenter Secure Control Module (DC-SCM). This modular structure allows for the separation of the computing platform from security and management functions, enabling independent development and adaptation to different server configurations.
Specific details regarding the exact FPGA family to be used, their logic capacity, power consumption, or clock frequencies have not yet been disclosed.
Гика
