MYBIGGAMING
LIVE
Agothic
Hardware 11 August 2026 2 min read

Intel Unveils Diamond Rapids with 256 Cores to Challenge AMD's Epyc Venice

Intel's upcoming Diamond Rapids server lineup will feature up to 256 P-cores, directly competing with AMD's Epyc Venice architecture in the next generation of data center CPUs.
Author: Гика PC
Intel Unveils Diamond Rapids with 256 Cores to Challenge AMD's Epyc Venice
Intel has revealed details about its next-generation server processor lineup, Diamond Rapids. Scheduled for release in 2027, this platform will be built on the Panther Cove architecture and serves as the successor to the current Xeon 6 (Clearwater Forest) series. The headline news is the confirmation of up to 256 Performance cores (P-cores) in the high-end variant, placing Intel on par with AMD's upcoming Epyc Venice generation.

Unlike previous iterations that relied on energy-efficient E-cores or hybrid configurations, Diamond Rapids will consist exclusively of performance cores. While insiders previously speculated about 192 cores, current data points to a configuration with 256 cores for the high-performance platform.

Technically, the new platform will feature the LGA9324 socket, support for up to 16 DDR5 memory channels (or MRDIMM), and the PCIe 6.0 interface. The maximum Thermal Design Power (TDP) is set at 500W, comparable to the current flagship Xeon 6980P.

A significant departure from previous generations will be the absence of Hyper-Threading (SMT). According to leaks and Intel documents, this feature will return only with the subsequent Coral Rapids generation. This decision aims to improve real-world single-core performance by reducing overhead costs.

The situation looks challenging for competitors. AMD has already announced the release of Epyc Venice (Zen 6 architecture) in the second half of 2026. The flagship Epyc 9996 will also feature 256 cores, indicating a direct clash between the two giants of the server market as early as next year.

It is worth noting that Intel has confirmed the use of the Intel 18A process for Compute Tiles, which should ensure high energy efficiency at such high core density. However, the lack of SMT and the transition to a new architecture will require system integrators to rethink their software optimization approaches.

Article author

Гика

Quick actions