Nova Lake Die-Shots: Intel to use TSMC N2P for Compute Tiles

Modular Design and Manufacturing Split

Following the precedent set by Arrow Lake, Nova Lake processors will be composed of multiple functional tiles. This modular approach allows Intel to scale its product stack across different segments, from mobile devices to high-end desktops.

Analysis of the die-shots for the mobile Nova Lake-H and HX variants reveals the following component breakdown:

• Graphics Tile: built on the Intel 3-E process, featuring 4 Xe-K cores.
• Hub Tile: manufactured on Intel 18A-P, including 4 LPE (Low Power Efficiency) cores.
• Peripheral Controller Tile: also produced on Intel 18A-P.
• Compute Tile: the primary processing unit, which is expected to be manufactured by TSMC on the N2P node.

For the HX configuration (8P+16E cores), the compute tile is estimated to be 6.5 x 16 mm, while the H version (4P+8E cores) will use a smaller 6.5 x 8,5 mm tile.

The Role of Intel 18A and TSMC

A key takeaway is Intel's hybrid manufacturing strategy. While the company is leveraging its own foundries for components like the Graphics Tile (using Intel 3 in smaller versions), it remains reliant on TSMC for the most advanced logic.

According to reports from leaker Jaykihn, the production rollout may involve a transition in nodes. Early Engineering Samples (ES1) are expected to be produced on Intel 18A-P for OEM validation. However, subsequent stages, including ES2 and Qualification Samples, are likely to move to TSMC N2P. This shift suggests that while Intel 18A-P is used for early-stage development, TSMC's process is preferred for meeting the performance and volume requirements of the final mass-market products.

For the desktop-oriented Nova Lake-S, the architecture is expected to follow a similar pattern. The high-end 52-core configuration (16P+32E+4LPE) will likely utilize two Compute Tiles to achieve its massive core count.