Unknown x86-Firma reports new WBINVD prefixes – cache extensions already in use
The x86 ecosystem is typically viewed as a closed loop dominated by Intel and AMD, yet recent signals from the Linux kernel mailing list suggest otherwise. An anonymous corporate entity, explicitly identified only as an "x86-Firma" (unknown x86 firm) other than the industry giants, has begun actively utilizing new instruction prefixes for the WBINVD command. These changes, which allow for selective cache invalidation to optimize performance, have reportedly been in use since 2025, marking a significant shift in how cache hierarchies are managed on modern silicon.
The core of this development lies in the WBINVD instruction itself, which stands for "Write Back and Invalidate Cache." Traditionally, this privileged x86 command flushes all modified data from the cache back to main memory and invalidates the entire cache hierarchy. However, the new prefixes introduced by the unknown firm allow developers to bypass specific levels of this process. For instance, prefix 0x67 skips the L0i- and L1i-instruction caches, while 0x66 targets the data caches (L0d/L1d). Other prefixes like 0xF2 and 0xF3 allow skipping the Last-Level Cache or the invalidation step entirely.
Beyond these specific optimizations, the firm has defined six additional implementation-specific prefixes: 0x26, 0x2E, 0x36, 0x3E, 0x64, and 0x65. These codes are reserved for distinguishing between code, data, and streaming stores or addressing different cache levels. Theoretically, these binary hints can be combined in up to 64 ways, potentially extending the WBINVD instruction to twelve bytes. This granularity suggests a sophisticated approach to memory management that avoids the performance penalty of a full system-wide flush.
This is not an isolated incident. Earlier reports from October 2025 indicated that this same entity was already using reserved x86 opcode, CPUID, and MSR ranges to avoid collisions with future definitions. More recently, in July 2026, similar signals emerged regarding AMX/ACE implementations supporting 16 or 32 tiles, a significant departure from Intel's current eight-tile architecture. While the technical patterns are consistent—selective cache handling, proprietary CPUID areas, and expanded tile support—the identity of the manufacturer remains officially unconfirmed.
Speculation about whether this is a new desktop competitor to Ryzen or Core is premature. The entity could be developing specialized server processors, internal hyperscaler systems, or accelerators that never reach the consumer market. What is confirmed is that these are not theoretical placeholders but active implementations in silicon. The existence of real x86 extensions known only through mailing lists and reserved codes represents a tangible shift in the hardware landscape, proving that innovation in the x86 space continues even outside the traditional powerhouses.
For now, the focus remains on the technical reality rather than corporate branding. The selective cache treatment demonstrated by these new prefixes offers a clear performance advantage for specific workloads, bypassing unnecessary memory writes. Until the developer reveals their identity or releases a product, this remains an interesting but anonymous trail in real silicon, confirming that the x86 instruction set is evolving with contributions from unexpected sources.
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