Intel Core Ultra 4000 Nova Lake-H CPU pictured, packing 16 cores
A leaked image of what is purported to be an Intel Nova Lake-H mobile processor has surfaced, offering a rare look at the modular architecture behind the upcoming Core Ultra 4000 series. The leak, shared by leaker momomo_us on X, provides a visual representation of the chip's multi-tile design, suggesting a highly segmented approach to silicon manufacturing.
The image, though low in resolution, allows for a clear distinction between several functional blocks. The chip appears to consist of six distinct tiles, which are likely dedicated to compute, graphics, the SoC/hub, and peripheral control. This modularity is a key part of Intel's strategy to increase flexibility in CPU configurations while managing production costs. By splitting the processor into separate tiles, Intel can manufacture complex components on the most advanced nodes while using older, more cost-effective processes for less demanding parts, such as the I/O or peripheral controllers.
A Hybrid Tile Architecture
According to the details surrounding this leak, the Nova Lake-H CPU is expected to feature a 16-core configuration. This setup reportedly includes four P-Cores, eight E-Cores, and four LPE-Cores, supported by 18MB of cache. The architecture is expected to utilize a mix of manufacturing nodes to optimize performance and yield. Specifically, the main compute tile containing the P-Cores and E-Cores is rumored to be built on TSMC’s N2P node. Meanwhile, the four LPE-Cores are expected to reside on the hub/SoC tile, manufactured using Intel’s 18A-P process.
The graphics component is also expected to be decoupled. The leak suggests the presence of four Xe graphics cores housed in a dedicated graphics tile, potentially utilizing Intel’s 3-E node. The remaining tiles would likely handle peripheral control on the 18A-P process, with the final two tiles acting as dummy silicon to maintain structural rigidity. However, it is worth noting that in higher-end models—such as a rumored Core Ultra 4970H with 12 Xe graphics cores—these dummy tiles might be replaced with active silicon to boost performance.
Estimated Die Sizes and Dimensions
Based on previous reports from Moore’s Law Is Dead, the total area of the chip is estimated to be approximately 276mm². The breakdown of the individual tiles is projected as follows:
This tile-based approach offers Intel significant scalability. By adjusting the number of cores or graphics units within the existing tile framework, the company can produce a wide range of processors without needing to design entirely new silicon from scratch. While the actual market competitiveness of the Nova Lake-H series remains to be seen, the technical roadmap suggests a sophisticated evolution of Intel's mobile computing lineup.
Гика
