Google reportedly taps AMD to design next-generation TPU — hybrid AI ASIC could integrate on-package CPU cores for reinforcement learning

A hybrid approach for reinforcement learning

Analysts at SemiAnalysis, cited by Sean, believe that market chatter suggests Google is working with AMD on a TPU project in the v10 generation. "AMD's involvement would be the first real involvement in a custom AI ASIC project, despite having a custom silicon team," the note reads. "AMD has strong IP, especially in advanced packaging and SoIC. Additionally, CPU IP could also be a draw given Google and its customers are pushing for TPUs with on-package CPU cores for RL workloads."

Unlike conventional LLM training, which remains overwhelmingly accelerator-heavy, reinforcement learning for reasoning and agentic models can require considerably more general-purpose compute around accelerator operations. This is where AMD comes into play, as it already has experience developing a data center-grade design — the Instinct MI300A — that packs both x86 and accelerator chiplets.

Context from previous TPU generations

Having developed nine generations of its proprietary AI accelerators (with Broadcom acting as actual silicon designer) and possessing extensive expertise in accelerator architecture, Google hardly needs AMD to design a conventional TPU. Hence, chances that AMD will implement Google's TPU v10i for inference or V10t for training are low.

Google has already begun to increase CPU resources around its latest inference-oriented TPUs. Its TPU 8i systems, designed for inference, reasoning, and RL workloads, feature one Google Axion CPU for every two TPUs. By contrast, servers running Google's 7th Generation TPUs used one Xeon 'Emerald Rapid' processor for every four TPUs. Furthermore, we are hearing that in some cases a 1:1 ratio of CPUs to accelerators is optimal, so the future of AI may be way more CPU-heavy than we think.

AMD's role and potential alternatives

Bringing CPU cores directly into the TPU package could be a logical next step, as reducing the distance between general-purpose and tensor compute can improve performance and reduce power consumption. A hypothetical Google design could therefore combine Google-developed TPU compute chiplets with AMD CPU and HBM in a tightly integrated package built by AMD.

Note that for now we are speculating and our analysis may be inaccurate. For now, the nature of AMD's alleged involvement remains unclear. Yet, if the report is indeed accurate, the important development may not be that AMD is helping Google build another TPU. Instead, what matters is that Google is considering a new CPU-heavy member of its TPU v10 family, optimized specifically for RL and agentic workloads, and is using AMD as a provider of some of the building blocks needed to create it.