CUDA 13.5 Brings Vera Rubin to General Availability: NVIDIA Enhances Scheduling and Multi-GPU Communication

The transition of the Vera Rubin platform to General Availability is the headline feature of this release. By moving out of the Early Access phase, NVIDIA is signaling that the software stack is now stable enough for developers to build and optimize production-grade workloads specifically for the Vera Rubin architecture. This is a crucial step for data center operators and AI researchers who require a reliable programming model for next-generation hardware.

Granular Control Over SMs and Multi-GPU Interconnects

A major focus of CUDA 13.5 is the refinement of resource management in shared environments. NVIDIA is introducing tighter integration between Locality Domains and the Multi-Process Service (MPS). Specifically, CUDA can now link cgroup-v2 structures with MPS namespaces, allowing administrators to automatically assign workloads to different resource policies. This eliminates the need to manually configure individual processes via separate environment variables. Furthermore, the update introduces Streaming Multiprocessor (SM) partitioning per namespace; once a specific SM partition is assigned to a namespace, all clients within that namespace inherit the same configuration. This is particularly vital for multi-tenant GPU systems where multiple services or users share a single accelerator instance.

To address reliability in resource monitoring, NVIDIA has added polling-based memory monitoring. In scenarios where cgroup notifications regarding memory limits are missing or unreliable, MPS can now directly query current usage before making decisions regarding resource eviction or release. While this adds a layer of management overhead, it reduces dependency on external notification systems.

Advancements in CUDA Tile and Memory Operations

The most impactful architectural change involves CUDA Tile. Within a Tile kernel, CUDA 13.5 now enables direct access to the memory of another GPU connected via NVLink. This is achieved through Unicast-pointers for addressing a single neighbor, and Multicast-pointers or specialized Multimem operations for distributing or reducing data across NVSwitch fabrics. By merging communication and computation within the same kernel, NVIDIA aims to reduce latency and synchronization overhead—a critical requirement for large-scale AI models where tensors are distributed across multiple accelerators.

Additionally, CUDA Tile now offers a preview of interoperability with traditional SIMT (Single Instruction, Multiple Threads) code. Tile kernels can directly call Device functions from SIMT libraries while data resides in registers or Shared Memory. Previously, these components had to be linked via separate kernels and global memory. For mathematical libraries, the updates for Vera Rubin include new heuristics and kernels in cuBLAS for NVFP4 and MXFP8 matrix operations, specifically targeting Mixture-of-Experts (MoE) workloads. For the Blackwell architecture, NVIDIA reports improvements of up to 1.5× for certain native FP64-SYRK and HERK operations, with cuSPARSE promising even larger gains depending on the algorithm. It is important to note that these figures apply to specific library operations and are not intended as a generalized metric for overall GPU acceleration.

Driver Model Changes for Rubin

The release also brings a shift in the driver model for the Rubin platform on Windows. While CUDA continues to support WDDM and Microsoft's Compute Driver Model (MCDM), the TCC (Tesla Compute Cluster) mode will no longer be supported on Rubin and subsequent GPU generations. Software that currently relies exclusively on TCC will need to be adapted for these future platforms.